The present invention generally relates to a method of fabricating a semiconductor apparatus, and more specifically, to a method of fabricating a semiconductor apparatus including plural saddle-fin transistors to reduce operating defects due to mis-alignment.
Generally, a semiconductor is a material that belongs to a middle region between a conductor and a nonconductor depending on electric conductivity. Although the semiconductor is similar to the nonconductor in a pure state, the electric conductivity of the semiconductor is enhanced by addition of impurities or other manipulation. With added impurities and connected to the conductor, the semiconductor is useful for manufacturing semiconductor devices. A semiconductor apparatus refers to apparatus that has various functions obtained by using the semiconductor device. A representative example of the semiconductor device is a semiconductor memory apparatus.
The semiconductor memory apparatus includes a plurality of unit cells each having a capacitor and a transistor. A capacitor is used to store data temporarily, and a transistor is used to transmit data between a bit line and the capacitor in response to a control signal (word line) by using a semiconductor property, that is the electric conductivity changing depending on environment. The transistor includes a gate, a source and a drain, and charges move between the source and the drain in response to the control signal inputted into the gate. The movement of charges between the source and the drain is performed through a channel region by using the semiconductor property.
When a general transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped in both sides of the gate to form a source and a drain. Due to an increase in the data capacity and integration of the semiconductor memory apparatus, the size of each unit cell is required to be smaller. That is, the design rule of the capacitor and the transistor in the unit cell is decreased. Likewise, the channel length of the cell transistor is reduced leading to the so-called short channel effect and a drain induced barrier lower (DIBL) effect in the transistor, thereby degrading the reliability of the operation. The short channel effect and the DIBL effect can be prevented when a threshold voltage is maintained so that the cell transistor may perform a normal operation. Generally, as the channel of the transistor becomes shorter, the doping concentration of impurities in the channel-forming-region is increased.
However, as the design rule is reduced to less than 100 nm, the increase of the doping concentration in the channel region increases an electric field of the storage node (SN) junction, degrading a refresh characteristic of the semiconductor memory apparatus. For prevention of the degradation, although the design rule is decreased, a cell transistor having a three-dimensional channel structure where the channel is vertically extended has been used so as to maintain the channel length of the cell transistor. That is, although the horizontal channel width is short, the doping concentration can be decreased corresponding to the vertical channel length to prevent the degradation.